1. Field of the Invention
The invention relates to a DRAM cell arrangement with vertical MOS transistors, and to a method for its fabrication, in which the transistors do not have any floating bodies, but rather are to be fully depleted.
2. Description of the Related Art
Currently, the memory cell used in a DRAM cell arrangement, i.e. a dynamic semiconductor memory, is almost exclusively the single-transistor memory cell, which has long been known and comprises an MOS select transistor and a capacitor. The information in the memory cell is stored in the form of a charge on the capacitor. The capacitor is connected to the transistor in such a way that, when the transistor is driven via a word line, the charge of the capacitor can be read out via a bit line.
In general, it is attempted to produce a DRAM cell arrangement which has a high packing density. In this respect, it is advantageous to design the MOS transistor as a vertical transistor, in which source, channel region and drain are arranged above one another. An MOS transistor of this type can take up a small amount of space irrespective of a channel length. Furthermore, it is attempted to arrange the vertical transistor and the associated capacitor of each memory cell vertically above one another on a semiconductor substrate.
An arrangement comprising a large number of memory cells of this type is known, for example, from DE 44 30 483 A1. Each memory cell has a column-like, vertically arranged select transistor, which includes a drain region and a source region in a semiconductor substrate column, with a current channel, which likewise runs in the vertical direction, running between the drain region and the source region, which current channel is controlled by a control gate electrode which completely surrounds the substrate column, separated by a layer of oxide. The control gate electrodes (which consist, for example, of doped polysilicon) of various memory cells are electrically connected to one another and form the word line for driving the select transistor.
A particular problem of the known MOS transistor is the column-like channel region, which is insulated from the substrate and in which charge carriers collect, which may, for example, alter the threshold voltage. The complete insulation of the active region, which is also present, for example, in SOI (Silicon-on-Insulator) substrates, where it has a number of advantages, accordingly also leads to negative effects, known as floating body effects. These effects are caused by the fact that charge carriers produced in the active region cannot flow out. This applies in particular to charge carriers produced in a channel region of a MOS transistor.
On the other hand, in the known MOS transistors, despite the gate electrodes surrounding the channel region it is not ensured that the depletion zone extends from the periphery of the column-like channel region all the way to its center, i.e. it is not certain whether the MOS transistor is actually fully depleted in the sense of a depletion zone which completely fills the channel region.
A MOS transistor of the fully depleted type, which is increasingly desired on account of its benefits, appears to be achievable only in situations in which the p-doped channel region is limited in some way, unlike in the case of the planar standard MOS transistor (in which it is not separated from the substrate). This is the case, for example, for the column-like channel region of the known transistor or also in the case of a planar MOS transistor on an SOI substrate. In these cases, however, the fact that the connection of the channel region to the substrate is absent on account of the insulation, on the other hand, has been found, as described above, to in fact lead to a situation with a floating body.
DE 199 29 211 A1 has disclosed a DRAM cell arrangement and a fabrication method in which the MOS transistors are designed as vertical transistors and in which floating body effects are avoided. The transistor described in that document forms a hump-like projection in the substrate with a laterally adjoining gate electrode, while on the other side of the projection the channel region is electrically connected to the gate electrode via a conductive structure, so that charge carriers produced in the channel region can flow away. The overall result in this known cell arrangement, however, is a complicated, interwoven structure which is correspondingly complex to fabricate.
The invention is based on the object of providing a DRAM cell arrangement and a method for its fabrication which provides transistors of the fully depleted type as far as possible without floating bodies, and, at the same time, ensures a simple fabrication process.